2018年12月18日（周二） 2:00-3:10 p.m.
Started with the commercialization of microprogramming and binary compatibility in 1960s led by IBM, there have been three waves of innovation in computing in the past 50 years. Since late 1970s, the advancement of integrated circuit technologies has been driven fast development of microprocessors with 60% annual performance improvement in 90s. However, with the end of Dennard Scaling and Moore’s Law, the sequential performance of modern microprocessor has improved poorly recent years. The architecture challenges are even harder given we have lost the exponentially increasing resources granted by Dennard Scaling and Moore’s law.
In order to continue scaling, it requires innovations on both novel computer architectures and post Moore’s law semiconductor technologies, such as domain specific architecture (DSA), silicon photonics and novel non-volatile memory technologies. All of these progresses require changes to the instruction set architecture (ISA). Historically, ISAs have been proprietary that involve very complicated legal work prior to any meaningful research and development. RISC-V, the fifth generation Berkeley RISC architecture, is a free and open ISA that allows many people in many organizations can innovate without any restriction. RISC-V is also designed for modularity and extensions that make novel energy-efficient DSA implementations truly possible.
In this talk, we will present the 28nm Pygmy SoC, a RISC-V based energy-efficient SoC for edge AI applications. Applying agile chip development methodologies, Pygmy has been designed by a small group of engineers within just 7 months from scratch to tape-out. Though highly software programmable, the energy efficiency of Pygmy’s integer vector engine beats that of the first-generation Google TPU by 1.7x. We believe open RISC-V ISA has opened up many opportunities for future innovations in computing. We envision the upcoming decade will be a golden age for computer architecture, which architects are freed from the chain of proprietary ISAs.
Dr. Zhangxi Tan is currently the CEO and Co-founder of OURS Technology Inc. Dr. Tan received his PhD in computer science from UC Berkeley with Prof David Patterson, 2017 Turing award winner and the inventor of RISC. He received his BE in EE from Tsinghua University. Dr. Tan is specialized in computer architecture and VLSI designs. After graduating from Berkeley in 2013, he joined Pure Storage (NYSE: PSTG, a startup then) as a Founding Engineer, also the first chip designer hired by Pure. Dr. Tan served as a lead designer for Pure’s award winning FlashBladeTM product, which generates hundreds of million-dollar revenues every year and have many high-profile customers like Tesla and Mercedes F1 racing team. Dr. Tan holds more than 20 US patents in flash storage systems and hardware accelerators.